(1) Field of the Invention
The present invention relates to a delay circuit in which the output signal is delayed by a specified time interval with respect to the input of both a rising edge and a falling edge, and able to work reliably and to obtain a sufficient delay time at a low power source voltage.
(2) Description of the Related Art
Generally, in digital circuits, it is frequently necessary to change the transmission time of the signal, i.e., a plurality of signals should be transmitted t the same time or should be transmitted at predetermined intervals, and a digital circuit is used for transmitting the signals at predetermined intervals.
Known conventional delay circuits are composed of switching transistors, such as FET's. FIG. 1, 2, 3, and 4 show typical prior art delay circuits composed of FET's, and to delay the signal, a Schmitt trigger circuit is used in the circuits of FIGS. 1 and 2, a network of capacitors and resistors (CR network) is used in the circuit of FIG. 3, and a multistage inverter circuit is used in the circuit of FIG. 4. Note, the FET's marked o in the drawings are P-channel FET's.
In the circuit of FIG. 1, the Schmitt trigger circuit 10 is composed of two P-channel FET's 11, 12 and two N-channel FET's 13, 14. The P-channel FET 11 and N-channel FET's 13 and 14 are connected in series between a high level constant power supply Vcc and a low level constant power supply Vss. The P-channel FET 12 is connected between the high level constant power supply Vcc and a node N.sub.2, which serves as a connecting point for the N-channel FET's 13 and 14. The gates of the FET's 11, 12, 13, and 14 are connected to the input terminal IN, and a node N.sub.1 is connected to the output terminal OUT of the Schmitt trigger circuit 10.
When the input terminal IN is low level, the P-channel FET's 11 and 12 are ON (conduction occurs between the source and drain) and the N-channel FET's 13 and 14 are OFF (no conduction occurs between the source and drain), and thus the nodes N.sub.1 and N.sub.2 are high levels. When the level changes from low level to high level at the input terminal IN, the P-channel FET's 11 and 12 become OFF and the N-channel FET 14 becomes ON immediately the input level passes the threshold voltage, but the N-channel FET 13 cannot become ON at the same time because the nodes N.sub.1 and N.sub.2 are both high levels. The N-channel FET 13 becomes ON after the node N.sub.2 is connected to the low level constant power supply Vss through the N-channel FET 14 and the level thereof becomes low. A delay occurs while the node N.sub.2 is changed from high level to low level, which supplies the threshold voltage to the gate of FET 13 after the N-channel FET 14 becomes ON. When the N-channel FET 13 becomes ON, the level of the output terminal OUT is changed from high level to low level. Accordingly, the change of the level from low to high at the input terminal IN is transmitted to the output terminal OUT in the opposite direction at a predetermined interval.
In FIG. 2, the Schmitt trigger circuit 20 is composed of two P-channel FET's 21 and 22 and two N-channel FET's 23 and 24. The P-channel FET's 21 and 22 and N-channel FET 23 are connected in series between a high level constant power supply Vcc and a low level constant power supply Vss. The N-channel FET 24 is connected between the low level constant power supply Vss and a node N.sub.3 which serves as a connecting point for the P-channel FET's 21 and 22. The gates of the FET's 21, 22, 23, and 24 are connected to the input terminal IN, and a node N.sub.4 is connected to the output terminal OUT of the Schmitt trigger circuit 20.
When the input terminal IN is high level, the N-channel FET's 23 and 24 are ON and the P-channel FET's 21 and 22 are OFF, and the nodes N.sub.3 and N.sub.4 are low levels. When the level changes from high level to low level at the input terminal IN, the N-channel FET's 23 and 24 immediately become OFF and the P-channel FET 21 becomes ON, but the P-channel FET 22 cannot become ON immediately because the nodes N.sub.3 and N.sub.4 are both low levels. Therefore, the P-channel FET 22 becomes ON after the node N.sub.3 is connected to the high level constant power supply Vcc through the P-channel FET 21 and the level thereof becomes high. A delay occurs while that the node N.sub.3 is changed from low level to high level after the P-channel FET 21 becomes ON. When the P-channel FET 22 becomes ON, the level of the output terminal OUT is changed from low level to high level, then in the same way as described in FIG. 1, the change of the level from high to low at the input terminal IN is transmitted to the output terminal OUT in the opposite direction at a predetermined interval.
In FIG. 3, the delay circuit 30 is composed of two inverters 31 and 33, and a CR network 32. Each of the inverters 31 and 33 comprises a P-channel FET and an N-channel FET connected in series between a high level constant power supply Vcc and a low level constant power supply Vss. The CR network 32 comprises two capacitors C.sub.1 and C.sub.2, and a resistor R.
When the input signal is low level, the input signal to the CR network is high level, and accordingly the capacitor C.sub.2 is charged and the capacitor C.sub.1 is discharged. When the signal changes from low level to high level at the input terminal IN, the signal at the output of the inverter 31 is changed from high level to low level, thereby discharging the capacitor C.sub.2 and charging the capacitor C.sub.1. As a result, the signal input to the CR network 32 is sent to the output of the CR network 32 after a predetermined delay, in accordance with the time constant defined by capacitors C.sub.1 and C.sub.2, and the resistor R. This delayed signal is then inverted by the inverter 33. When the signal changes from high level to low level, the delay operation in this circuit 30 is also carried out, and accordingly, the signal to the input terminal IN is transmitted to the output terminal OUT at a predetermined interval.
In FIG. 4, the delay circuit 40 is composed of a multistage inverter, i.e., the delay circuit 40 comprises a plurality of inverters 41, 42, . . . 4n. Each inverter comprises a P-channel FET and an N-channel FET connected in series between a high level constant power supply Vcc and a low level constant power supply Vss. In this delay circuit 40, a signal input to the input terminal IN is delayed by each inverter circuit, due to a switching time lag thereof. The delay time is defined by the number of inverters in the delay circuit 40.
In the delay circuits shown in FIGS. 1 and 2, the delay operations can be carried out for a one way change of the input signal. Namely, the Schmitt trigger circuit 10 shown in FIG. 1 delays the input signal only upon a change from low level to high level, and the Schmitt trigger circuit 20 shown in FIG. 2 delays the input signal only upon a change from high level to low level FIGS. 5A, 5B, and 5C shown waveforms for explaining the operation of the delay circuit as shown in FIGS. 1 and 2 when the voltage of the high level constant power supply Vcc is 5 V. In FIG. 5A, the waveform indicates a signal input to the input terminal IN of the circuits 10 and 20. The input signal changes at time t.sub.1 and time t.sub.2. In FIG. 5B, the waveform indicates a signal output from the output terminal OUT of the circuit 10, and in FIG. 5C, the waveform indicates a signal output from the output terminal OUT of the circuit 20. FIG. 6A, 6B, and 6C show waveforms for explaining the operation of the delay circuit as shown in FIGS. 1 and 2 when the voltage of the high level constant power supply Vcc is less than 3 V, for example, 1.5 V. In FIG. 6A, the waveform indicates a signal input to the input terminal IN of the circuits 10 and 20. The input signal changes at time t.sub.1 and time t.sub.2. In FIG. 6B, the waveform indicates a signal output from the output terminal OUT of the circuit 10, and in FIG. 6C, the waveform indicates a signal output from the output terminal OUT of the circuit 20. From FIGS. 5B, 5C, 6B, and 6C, it is clearly understood that the circuit 10 shown in FIG. 1 delays the input signal only upon a change from low level to high level, and the circuit 20 shown in FIG. 2 delays the input signal only upon a change from high level to low level.
In the delay circuit shown in FIG. 3, a delay operation can be carried out for a rising or falling input signal at the input terminal IN, as shown in FIGS. 5A and 5D, when the voltage of the high level constant power supply Vcc is 5 V. Conversely, in the delay circuit shown in FIG. 3, the delay time is not stable when the voltage of the high level constant power supply Vcc is less than 3 V, for example, 1.5 V, because the response of the CR network is blunted under the low voltage condition, as shown in FIG. 6D. Further, when the response of the CR network is blunted, a wave shaping circuit must be included for compensating the weakened output signal.
In the delay circuit shown in FIG. 4, however, defects described above do not exist, but instead, it is necessary to accumulate among inverters on the semiconductor tip to obtain a predetermined interval, because the delay at each inverter is very slight, and thus the circuit scale is increased. Further, an increase in the number of inverters leads to an increase in the power consumption.